The present invention relates to a semiconductor memory device. In particular, the present invention relates to a semiconductor memory device having also a low electric power characteristic.
In general, as regards a dynamic memory, which stores information by charge accumulated in a capacitor, it is necessary to perform refresh operation in order to hold information in the memory. During the refresh operation, power is supplied to the memory, and data in the memory is read and rewritten at intervals of about 64 ms. FIG. 3 shows a time relation of power-on. A horizontal axis indicates time; tREF represents a period during which refresh operation is being performed; tNOM represents a period during which the refresh operation is not performed; and PWRPM represents a period during which power supply is being turned on. Such an example is shown in, for example, xe2x80x9cHitachi IC Memory Data Book 2xe2x80x9d, Hitachi, Ltd., pp. 239, September 1997.
On the other hand, as regards an EEPROM and a flash memory, which stores information by electrons accumulated in a floating gate in general, information in the memory is held for about 10 years even if power is not supplied to the memory. Such an example is shown in, for example, xe2x80x9cHitachi IC Memory Data Book 3xe2x80x9d, Hitachi, Ltd., pp. 147, September 1996.
At present, a memory cell, which uses a data storage concept of a dynamic memory (DRAM: Dynamic Random Access Memory), is widely studied. There is a high possibility that a memory cell, which is capable of storing information even if a period for refresh operation is much longer (for example, 10 seconds) than the present refresh interval of about 64 ms, is developed.
In this case, in particular, the DRAM has a disadvantage of power consumption during a standby state.
FIGS. 3 through 5 are diagrams illustrating relations between refresh and power supply control when various memory elements are used. FIG. 3 illustrates a relation found in the conventional DRAM; FIG. 4 illustrates a relation found when a memory element, of which a period for refresh operation is longer than the present refresh interval of about 64 ms, is used; and FIG. 5 illustrates a relation according to the present invention. By the way, in these diagrams, tREF represents a period for refreshing memory; tNOM represents a standby period; and PWRON represents a period during which power supply is being turned on.
To be more specific, for example, if a dynamic memory of which a period for refresh operation is 10 seconds could be realized, and if the conventional technique is used, the following operation is required to hold information accumulated in the dynamic memory: supplying power to the dynamic memory; and performing refresh operation once every 10 seconds. FIG. 4 shows a time relation of power-on of this example. A horizontal axis is time, and representations in FIG. 4 are the same as those shown in FIG. 3. The refresh operation requires a large amount of electric power (hereinafter referred to as refresh electric power). However, due to sub-threshold leakage current, electric current flowing into a constant current supply circuit, and the like, only supplying power to a circuit causes the circuit to consume a small amount of electric power (hereinafter referred to as standby power consumption).
As regards the DRAM of which characteristics are illustrated in FIG. 3, a ratio of the period tREF to the period tNOM is 1/6400. Because of it, the standby power consumption described above is little remarkable. However, on the other hand, in the method shown in FIG. 4, a ratio of the period tREF to the period tNOM is 1/1000000. Therefore, even if standby power consumption is 1/1000000 of refresh electric power, almost the same amount of electric power as the refresh electric power will be consumed in total as the standby power consumption.
In addition, also in the case of the flash memory, promoting miniaturization in a manufacture process, etc. causes film thickness of an oxide layer enclosing the floating gate to become thin, resulting in short data retention time. For example, if the data retention time becomes one year, and if the conventional technique is used, the flash memory will be used on the assumption that the data retention time of the flash memory is one year. This will cause degradation of a lifetime of the product.
Main means used to solve the above-mentioned problems will be described below.
The present invention relates to a semiconductor memory device comprising: a memory including a plurality of memory cells and a plurality of circuit blocks; a power switching means; and a refresh control apparatus; wherein: said semiconductor memory device has a first operation state and a second operation state; in the first operation state, the refresh control apparatus supplies power to the memory using the power switching means to refresh the memory cells; in the second operation state, the refresh control apparatus turns off the power supply to at least one circuit block of the memory using the power switching means; and an operation state, in which round transition between the first operation state and the second operation state is repeated multiple times, is provided.
What is important in the present invention is that in the second operation state, the power supply to at least one circuit block of the memory is turned off.
Moreover, although the round transition between the first operation state and the second operation state is repeated multiple times, the number of times is realistically considered as five times or more.
Furthermore, it is needless to say that, what is called, the DRAM, the flash memory, or other storage elements can be used as the memory cell according to present invention. A main point of the inventive concept of the present invention is a large reduction of the standby power consumption of the memory element. Therefore, as described above, if a memory cell having a characteristic that the period for refresh operation of the memory cell is much longer than that of the refresh interval (for example, for one second or more) is used, the present invention is extremely useful. If a memory cell, of which a period for refresh operation is longer than the above (for example, 10 seconds or more), is used, greater effect will be produced.
More specifically, the present invention is useful when using a memory cell having a characteristic that an interval between the first storage holding operation and the second storage holding operation of the memory cell is one second or more. Furthermore, the present invention is useful when using a memory cell having a characteristic that an interval between the first storage holding operation and the second storage holding operation of the memory cell is 10 seconds or more.
It is to be noted that the present invention is basically applied to a period over which only data holding is performed. In other words, as a matter of course, during operation such as read or write of the memory, etc., the power supply is not turned off. This can be understood judging from the point of the present invention, that is to say, the reduction of standby power consumption.
For the purpose of reducing the standby power consumption, there are a plurality of methods for turning off power supply of a desire element. Embodiments of these various methods will be described as below.